GPIF Streaming

The GPIF (General Programmable Interface) engine in the Cypress FX2 provides a hardware-managed data path from the BCM4500 demodulator to the USB host. After initial setup, no firmware intervention occurs in the data path — the GPIF engine reads transport stream data directly into the EP2 FIFO, and the AUTOIN mechanism automatically commits full packets to the USB controller.

Data Flow Architecture

                                  Cypress FX2 (CY7C68013A)
                               +-----------------------------+
                               |                             |
BCM4500          P3.5 TS_EN   |   GPIF Engine    EP2 FIFO   |   USB 2.0 HS
Demodulator  <-----------------+   (Master Read)  (AUTOIN)   +------------>  Host
 (I2C:0x08)     GPIF Data Bus |   0xE4xx wfm     4x buf     |   EP2 (0x82)
            ------------------->   CTL/RDY pins   8-bit      |   Bulk IN
            8-bit parallel TS  |                             |   7 URBs x 8KB
                               +-----------------------------+

Key Register Configuration

All values are identical across the three stock firmware versions (v2.06, Rev.2 v2.10, v2.13):

Register	Address	Value	Function
IFCONFIG	0xE601	0xEE	Internal 48 MHz clock, GPIF master, async, debug output
EP2FIFOCFG	0xE618	0x0C	AUTOIN=1, ZEROLENIN=1, 8-bit data path
REVCTL	0xE60B	0x03	NOAUTOARM + SKIPCOMMIT
CPUCS	0xE600	bits [4:3]=10	48 MHz CPU clock
FLOWSTATEA	0xE668	OR 0x09	FSEN (flow state enable) + FS[3]
GPIFIE	0xE65C	OR 0x3D	Waveform, TC, DONE, FIFO flag, WF2 interrupts

IFCONFIG Decode (0xEE = 1110_1110)

Bit	Name	Value	Meaning
7	IFCLKSRC	1	Internal clock source
6	3048MHZ	1	48 MHz IFCLK frequency
5	IFCLKOE	1	IFCLK pin drives output (clock to BCM4500)
4	IFCLKPOL	0	Non-inverted clock polarity
3	ASYNC	1	Asynchronous GPIF (RDY pin handshaking)
2	GSTATE	1	Debug state output on PORTE
1:0	IFCFG	10	GPIF internal master mode

The FX2 operates as a GPIF master, reading data from the BCM4500’s parallel transport stream output. Asynchronous mode means the GPIF uses RDY pin handshaking rather than clock-edge sampling.

EP2FIFOCFG Decode (0x0C = 0000_1100)

Bit	Name	Value	Meaning
4	INFM1	0	Packet count not decremented
3	AUTOIN	1	Auto-commit IN packets when FIFO buffer full
2	ZEROLENIN	1	Allow zero-length IN packets
1	(reserved)	0	—
0	WORDWIDE	0	8-bit data path (not 16-bit)

The AUTOIN bit is critical: when the GPIF fills an EP2 FIFO buffer to the configured packet size, the FX2 hardware automatically arms the buffer for USB transfer.

GPIF Waveform Configuration

The GPIF waveform descriptors occupy 128 bytes at 0xE400-0xE47F and are loaded from a compressed init table during firmware startup. The waveform programs a straightforward read cycle:

States 0-5: CTL outputs = 0x01 (control line asserted), 1 IFCLK each
State 6:    CTL = 0x07, length = 0 (idle/terminate)
Opcode:     0x00 (SDP = sample data point)
Output:     0xF0 (FIFO write flags)

This encodes a simple “assert read strobe, capture data, de-assert” cycle that reads one byte per GPIF transaction from the BCM4500’s parallel port into the EP2 FIFO.

FIFO Reset Sequence

All endpoint FIFOs are reset during initialization using the Cypress-prescribed procedure:

FIFORESET = 0x80;    // NAKALL: NAK all host transfers during reset
// 3-NOP SYNCDELAY
FIFORESET = 0x02;    // Reset EP2 FIFO
// 3-NOP SYNCDELAY
FIFORESET = 0x04;    // Reset EP4 FIFO
// 3-NOP SYNCDELAY
FIFORESET = 0x06;    // Reset EP6 FIFO
// 3-NOP SYNCDELAY
FIFORESET = 0x08;    // Reset EP8 FIFO
// 3-NOP SYNCDELAY
FIFORESET = 0x00;    // Release NAKALL

The triple-NOP delays (mandatory SYNCDELAY) between writes are required by the FX2 architecture: XRAM register writes take 2 cycles to propagate, and back-to-back writes to the same register need at least 3 instruction cycles.

ARM_TRANSFER Command (0x85)

The host issues vendor command 0x85 to start or stop the MPEG-2 transport stream. The handler checks the configuration status byte bit 0 (demodulator active) before proceeding.

Start Streaming
Stop Streaming

When wValue=1 and the demodulator is active:

Set streaming flag — config_byte bit 7 = 1 (bmArmed).
Load GPIF transaction count — GPIFTCB3:2 = 0x8000 (2 GB, effectively infinite).
Reset address and byte count — Clear GPIF address registers and EP2 FIFO byte count.
Assert TS_EN — P3.5 LOW (BCM4500 transport stream output enabled).
Wait for initial GPIF transaction — Poll GPIFTRIG bit 7 (DONE) until set.
De-assert TS_EN — P3.5 HIGH.
Trigger continuous GPIF read — GPIFTRIG = 0x04 (read direction, EP2 select).
Set streaming indicator — P0.7 LOW.

ORL   0x4e, #0x80      ; config_byte |= 0x80 (streaming flag)
MOV   DPTR, #0xE630    ; GPIFTCB3
MOV   A, #0x80
MOVX  @DPTR, A         ; GPIFTCB3 = 0x80 (huge transaction count)
; ... address/FIFO reset ...
ANL   0xb0, #0xDF      ; P3 &= 0xDF -> P3.5 = 0 (TS_EN assert)
; Poll GPIFTRIG.DONE ...
ORL   0xb0, #0x20      ; P3 |= 0x20 -> P3.5 = 1
MOV   0xbb, #0x04      ; GPIFTRIG = 0x04 (read EP2)
ANL   0x80, #0x7F      ; P0 &= 0x7F -> P0.7 = 0 (streaming)

When wValue=0 and currently streaming (config_byte bit 7 set):

Set stopped indicator — P0.7 HIGH.
Force-flush buffer — EP2FIFOBCH = 0xFF (skip current FIFO packet).
Wait for GPIF idle — Poll GPIFTRIG bit 7 (DONE) until set.
Discard partial packet — OUTPKTEND = 0x82 (skip bit set, EP2 select).
Clear streaming flag — config_byte bit 7 = 0.
De-assert control lines — P3 bits 7:5 = 1 (all BCM4500 controls idle).

ORL   0x80, #0x80      ; P0 |= 0x80 -> P0.7 = 1 (stopped)
MOV   DPTR, #0xE6F5    ; EP2FIFOBCH
MOV   A, #0xFF
MOVX  @DPTR, A         ; Force flush
; Poll GPIFTRIG.DONE ...
MOV   DPTR, #0xE648    ; OUTPKTEND
MOV   A, #0x82         ; Skip=1, EP2
MOVX  @DPTR, A         ; Discard partial packet
ANL   0x4e, #0x7F      ; config_byte &= 0x7F (clear streaming)
ORL   0xb0, #0xE0      ; P3 |= 0xE0 (de-assert all controls)

Interrupt Handling

INT4 and INT6 (GPIF/FIFO events) share a common handler that sets a software flag and clears EXIF.4:

PUSH  A
PUSH  DPH
PUSH  DPL
SETB  0x01               ; Set GPIF event flag (_0_1)
ANL   0x91, #0xEF        ; Clear EXIF.4 (INT4/INT6 IRQ flag)
MOV   DPTR, #0xE65D      ; GPIFIRQ
MOV   A, #0x01
MOVX  @DPTR, A           ; Clear GPIFIRQ bit 0
POP   DPL
POP   DPH
POP   A
RETI

The main loop polls this flag, enters CPU idle mode (PCON.0) between events, and checks EP2CS for buffer availability before re-arming the GPIF. The FLOWSTATE engine (FSEN=1) automatically re-triggers GPIF transactions when EP2 buffers become available.

GPIF Interrupt Enable (GPIFIE)

Bit	Name	Enabled	Purpose
0	GPIFWF	Yes	Waveform completion interrupt
1	(reserved)	No	—
2	GPIFTCEXP	Yes	Transaction count expired
3	GPIFGPIFDONE	Yes	GPIF operation done
4	GPIFFF	Yes	FIFO flag interrupt
5	GPIFWF2	Yes	Waveform 2 completion

Throughput Analysis

Metric	Value
USB 2.0 HS bulk (theoretical)	480 Mbps
USB 2.0 HS bulk (practical)	~280 Mbps (~35 MB/s)
GPIF engine (theoretical)	48 MHz x 8 bits = 384 Mbps
Typical DVB-S TS rate	1—5 MB/s
Maximum DVB-S2 rate (hypothetical)	~7.25 MB/s (58 Mbps)

The USB/GPIF path has approximately 5x headroom even at the maximum theoretical data rate. The bottleneck for all supported modes is the satellite link, not the USB data path.

Timing

Parameter	Value
GPIF clock	48 MHz internal
CPU clock	48 MHz
GPIF mode	Asynchronous (RDY pin handshaking)
NOP delays	3 NOPs between XRAM writes (~62.5 ns at 48 MHz)
EP2 buffer commit	Automatic via AUTOIN on FIFO fullness
GPIF re-trigger	Automatic via FLOWSTATE when EP2 buffer space available

Cross-Version Comparison

The GPIF streaming path is functionally identical across all three firmware versions. Only code addresses differ due to recompilation:

Aspect	v2.06	v2.13 FW1	Rev.2 v2.10
ARM_TRANSFER handler	CODE:0110	CODE:0110	CODE:00FA
GPIF control function	CODE:1919	CODE:1800	CODE:0D7C
Config byte IRAM	0x6D	0x4F	0x4E
EP2FIFOCFG value	0x0C	0x0C	0x0C
IFCONFIG value	0xEE	0xEE	0xEE
FLOWSTATEA setting	OR 0x09	OR 0x09	OR 0x09